1. Field of the Invention
The present invention relates to a data transmission circuit for compensating variations in data transmission speed between a start and an end portion of a data line. In particular, a circuit for minimizing time delay caused by resistive/capacitive loading of the data line through which data is transmitted.
2. Brief Description of the Prior Art
In development of a semiconductor device, a main issue concerns the development of integrated semiconductor devices of minimal size and capable of operating at high-speed.
When electronic devices operate at high speed, problems associated with high speed can occur. For example, a speed difference may occur at a data line having a large load. The speed difference may be due to a time delay in resistive/capacitive (RC) loading at the start and end portions of the data line connected with a driver output in transmission of data signals. Such a variation in speed is one factor lowering overall performance of semiconductor devices.
Variations in transmission speed caused by RC loading at the start and end portions of the data line connected with a driver output in transmission of data signals will be described in accordance with FIG. 1.
Referring to FIG. 1, the main data line driver 101 (hereinafter referred to as "MDL") is a driver for transmitting data signals, and a data line 102 transmits data signals sent from the MDL driver 101. MDL is a signal transmitted through the data line 102, including MDLn, a signal proximal to the MDL driver 101, and MDLf, a signal further from the MDL driver 101. In addition, MDL is pre-charged "high", which will be kept high by a latch part 103. When the MDL signal is enabled low, the latch part 103 turns "off", transmitting the MDL signal through the data line 102. The reset part 104 generates a signal RS-MDL1 to turn "on" a transistor Tl and pre-charge MDL "high" for a predetermined period of time after sensing that MDL is enabled low. The data line 102 connects the MDL driver 101 to a data output 105. At this time, if the data line 102 has a large loading capacity, there may be a time delay caused by RC, causing variation in the speed between MDLn and MDLf. FIG. 6 is a timing diagram of the signal of the circuit shown in FIG. 1 in which a speed difference occurs between MDLn and MDLf. As shown in FIG. 6, there is a time delay of .DELTA.t between MDLn and MDLf. The occurrence of the speed difference as such, ultimately brings about a speed push, lowering overall performance of the semiconductor device.
A solution proposed in the prior art is shown in FIG. 2. FIG. 2 shows a structure of a data transmission circuit constructed to solve the aforementioned problem of the speed difference occurring in FIG. 1. A re-buffer 202 is used for amplifying MDL and compensating for the speed push in the first compared embodiment, thereby reducing the time delay .DELTA.t. In the data transmission circuit shown in FIG. 2, there is an advantage in that the speed push resulting from the difference in speed can be compensated for, improving overall performance of a semiconductor device. However, the circuit of FIG. 2 results in a larger chip with the addition of a re-buffer to the data transmission circuit to compensate for the speed push. In other words, re-buffers are added to all the data lines, resulting in a larger chip. As a result, the re-buffers are not suitable for miniaturization of a chip, and are limitedly to products whose performance is regarded as more important than the size of a chip.